Generally, a DRAM device comprises a cell array area and a peripheral circuit area. The cell array area includes a plurality of unit cells, each of which comprises a MOS transistor and a storage capacitor. The storage capacitor comprises a lower electrode (i.e., storage node) and an upper electrode (i.e., plate node). It is a generally accepted fact in industry that the capacitance of the storage capacitor is required to be 0.25 μF or more, while the unit cell size has been constantly reduced for higher packing density of a DRAM device. One of approaches used to retain the required value of the capacitance is to increase the height of the storage capacitor. Especially in the case of a DRAM device with single cylinder type storage nodes and a design rule of 0.15 μm, the height of the storage node is required to be about 1.4 μm or more. The increased height of the storage node induces an increased step difference between the cell array area and the peripheral circuit area in the DRAM device.
Meanwhile, resistors are widely used in semiconductor memory devices including DRAM devices. The resistors are usually formed in the peripheral circuit area of a semiconductor memory device. One example of an application of the resistors is a circuit for converting an external voltage level into an internal voltage level. In DRAM devices, the resistors are usually formed of the same material as the plate node and are formed at the same process step for forming the plate node. In detail, a plate node layer is formed on storage nodes and a peripheral circuit area. The plate node layer is patterned to form a plate node on the storage nodes and resistors on the peripheral circuit area simultaneously.
However, in recent DRAM devices having high packing density, the patterns of the resistors are not fine. That is, it is very difficult to maintain uniformity in the widths of the resistors. The irregular widths induce irregular resistance of the resistors. As a result, abnormal operations of the DRAM devices may occur. The width irregularity problem is mainly due to the above-mentioned step difference between the cell array area and the peripheral circuit area.
The irregularity problem may be relieved by using a well-known advanced photolithography process that is able to pattern the plate node layer into quite fine patterns of resistors in spite of the increased step difference. However, the cost of the advanced process is too expensive such that it cannot be widely accepted in industry. Accordingly, the need to relieve the width irregularity problem without substantially increasing the cost for patterning the plate node layer remains.